In the “front-end” circuit design stage, designers choose device sizes of a given circuit topology, according to power consumption, area, performance, and yield goals. In “back-end” layout design, designers specify the geometric placement for each device, and the wire routing between devices. The layout is used as specifications how to manufacture the design in a semiconductor manufacturing process.
On modern semiconductors, “well proximity” effects are becoming more of an issue (see e.g., P. G. Drennan, M. L. Kniffin, “Implications of Proximity Effects for Analog Design,” Proc. 2006 IEEE CICC, September 2006, the contents of which are incorporated herein by reference). Well proximity effects occur because, during the CMOS manufacturing process, atoms can scatter laterally from the edge of the photoresist mask and become embedded in the silicon surface near the edges of the retrograde wells needed for latch-up protection and suppression of lateral punch-through. This causes the characteristics, such as the MOSFET electrical characteristics to vary with the distance of the transistor from the well-edge. The impact of well proximity effects is particularly severe at 90 nm and smaller process technologies.
Traditionally, there have been three ways to deal with proximity effects. The first way is to ignore them. FIG. 1shows an exemplary prior art method 100 of CMOS manufacturing whereby proximity effects are ignored. According to such a method, the manufacturing process occurs in the following steps: a circuit topology is designed 102, and then the devices required by that topology are sized 104. Devices are then placed and routed 106, after which a netlist is extracted and verified 108. A circuit is then built according to the netlist 110 and the circuit is then tested 112 for functionality. But in modern CMOS processes, this is a great risk because there is a chance that the proximity effects will kill the functionality of the circuit, which will result in a costly re-design and lost time to market. In the method shown in FIG. 1, for example, because the circuit design does not account for any well proximity effects, the resulting circuit 114 could potentially be non-functional due to, for example, threshold voltage drift in certain devices that arises from the devices' proximity to a well edge.
A second known approach to circuit design is known as “guardbanding.” Because it is not known at the circuit design stage which devices are sensitive to the effects, the designer uses heuristics to conservatively guard-band devices; i.e. each device is surrounded by a well with conservatively-wide safety margins. FIG. 2 shows an example of such method 200. The first steps of designing the topology 202 and sizing the necessary devices 204 proceeds as in FIG. 1. However, prior to netlist extraction and verification 208, this method introduces wide spacing 206 between each device sensitive to a proximity effect and the well edges in the circuit design. Unfortunately, this method results in area penalties.
A third prior art approach is shown in FIG. 3. According to this method, the circuit designer designs a circuit topology 302, sizes the necessary devices 304, places & routes the devices 306 and extracts a netlist from the determined layout as in the method set out in FIG. 1. Then, the designer simulates to determine if there are any proximity effect-related issues. If there are issues, the designer must alter the design, and repeat the process 307. Because the process is iterative, and done after layout, it causes design time penalties.
Besides proximity effects, there are other layout-style effects that are becoming more of a concern, including shallow trench isolation (STI) stress and channel stress. To handle these effects, designers currently use many of the techniques used to handle proximity effects: either guardbanding can be used, which causes area penalties; or an iterative process involving layout in the loop can be used, which causes design time penalties.